Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that uses magnetic elements. For example. Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT-RAM).
FIG. 1 illustrates a conventional STT-MRAM bit cell 100. The STT-MRAM bit cell 100 includes magnetic tunnel junction (MTJ) storage element 105, a MOS transistor 101, a bit line 102, source line 104 and a word line 103. The MTJ storage element is formed, for example, from at least two ferromagnetic layers (a pinned layer and a free layer), each of which can hold a magnetic field or polarization, separated by a thin non-magnetic insulating layer (tunneling barrier). Electrons from the two ferromagnetic layers can penetrate through the tunneling barrier due to a tunneling effect under a bias voltage applied to the ferromagnetic layers.
The magnetic polarization of the free layer can be reversed so that the polarity of the pinned layer and the free layer are either substantially aligned (parallel) or opposite (anti-parallel). The resistance of the electrical path through the MTJ will vary depending on the alignment of the polarizations of the pinned and free layers. This variance in resistance can be used to read the STT-MRAM bit cell 100. The STT-MRAM bit cell 100 also includes a sense amplifier 108, read/write circuitry 106 and a bit line reference 107. The operation and construction of the STT-MRAM bit cell 100 is known in the art and will not be discussed in detail herein. Additional details are provided, for example, in M. Hosomi, et al. A Novel Nonvolatile Memory with Spin Transfer Torque Magnetization Switching: Spin-RAM, proceedings of IEDM conference (2005), which is incorporated herein by reference in its entirety.
The STT-MRAM bit cell 100 may be programmed such that a binary value “0” is associated with an operational state wherein the polarity of the free layer is parallel to the polarity of the pinned layer. Correspondingly, a binary value “1” may be associated with an anti-parallel orientation between the two ferromagnetic layers. A binary value may thus be written to the bit cell by changing the polarization of the free layer. A sufficient current density (typically measured in Amperes/centimeter2) generated by the electrons flowing across the tunneling barrier is required to change the polarization of the free layer. Supply of current to the MTJ storage element 105 is controlled by the MOS transistor 101. Decreasing the resistance path through the MOS transistor 101, contributes to increasing the current supplied to the MTJ storage element 105 which leads to higher performance.
However, techniques to fabricate low resistance MOS transistors may involve increasing the area of the MOS transistors. The area of the STT-MRAM bit cell 100 is largely dependent on the area of the MOS transistor 101, because the area of the MTJ storage element 105 is very small in comparison. Hence, increasing the area of the MOS transistor 101 leads to a corresponding increase in the area of the STT-MRAM bit cell 100, which in turn leads to a lower number of STT-MRAM bit cell 100 per unit area of a memory array formed from STT-MRAM bit cells.
Accordingly, the area of the MOS transistor is a key parameter in the design and development of STT-MRAM arrays. High density STT-MRAM architectures may compromise on performance to pack more STT-MRAM bit cell 100 per unit area by decreasing the area of the MOS transistor 101.
On the other hand, high performance architectures, which require a greater supply of current to the MTJ storage element 105, may compromise on density by increasing the area of the MOS transistor 101. Alternately, the memory array may be designed such that an STT-MRAM bit cell may include a plurality of MOS transistors connected in parallel, driving a single MTJ storage element. Such arrangements with “n” transistors driving 1 MTJ storage element are commonly referred to as “nT-1MTJ” architectures.
It is difficult to control the size of the transistors with precision, during the initial development phase of such memory arrays. Further, test chips may require different fabrication databases to test memory architectures designed for high performance and memory architectures designed for high density. More particularly, conventional techniques require different databases for high density STT-MRAM bit cells with a single MOS transistor 101 and single MTJ storage element 105 (1T-1MTJ), and high performance STT-MRAM bit cells with nT-1MTJ architectures.